Projects: Difference between revisions
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=='''High Performance Processors: Techniques, Algorithms, and Tools'''== | =='''High Performance Processors: Techniques, Algorithms, and Tools'''== | ||
'''Abstract:'''This project aims at code generation algorithms and software simulators for high performance computer architecture. Specifically, we focus on new algorithms for instruction scheduling and register allocation coupled with the llvm compiler infrastructure based on the subgraph isomorphism scheduling. Moreover, we carry out software simulators for those high performance architectures. | |||
'''Team:''' | '''Team:''' | ||
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*Richard Steffano - undergraduate student | *Richard Steffano - undergraduate student | ||
*Thiago Machado - master student | *Thiago Machado - master student | ||
* | *Jader Perez - undergraduate student | ||
'''Sponsor:''' | '''Sponsor:''' CNPq | ||
=='''High Performance Processors: Hardware Synthesis'''== | =='''High Performance Processors: Hardware Synthesis'''== | ||
'''Abstract:'''This project aims at code generation algorithms and prototyping of encoding/decoding hardware resources for high performance computer architecture. Software toolchains supporting instruction encoding and code generation for those architectures is also a goal to be met. | |||
'''Team:''' | '''Team:''' | ||
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*Felipe Yonehara - digital ic designer | *Felipe Yonehara - digital ic designer | ||
'''Sponsor:''' | '''Sponsor:''' Fundect | ||
Revision as of 20:56, 2 June 2011
High Performance Processors: Techniques, Algorithms, and Tools
Abstract:This project aims at code generation algorithms and software simulators for high performance computer architecture. Specifically, we focus on new algorithms for instruction scheduling and register allocation coupled with the llvm compiler infrastructure based on the subgraph isomorphism scheduling. Moreover, we carry out software simulators for those high performance architectures.
Team:
- Ricardo R. Santos - coordinator
- Rubia M. de Oliveira Santos - researcher
- Lucas Silva - master student
- Richard Steffano - undergraduate student
- Thiago Machado - master student
- Jader Perez - undergraduate student
Sponsor: CNPq
High Performance Processors: Hardware Synthesis
Abstract:This project aims at code generation algorithms and prototyping of encoding/decoding hardware resources for high performance computer architecture. Software toolchains supporting instruction encoding and code generation for those architectures is also a goal to be met.
Team:
- Ricardo R. Santos - coordinator
- Rodolfo Azevedo - researcher
- Milton Romero - researcher
- Evandro Martins - researcher
- Renan Marks - master student
- Renato Fernando dos Santos - master student
- Felipe Oliveira - undergraduate student
- Marcel Grassi - undergraduate student
- Felipe Yonehara - digital ic designer
Sponsor: Fundect
